A flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, a group of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to thereby program the cell with a binary 1 or 0, to read the cell, to erase all or some of the cells as a block, to verify that the cell is erased or to verify that the cell is not over-erased.
Memory cells in a flash memory device are typically connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in a column being connected to a respective bit line. The sources of all the cells may be connected together.
A cell is typically programmed by applying a voltage to the control gate, applying a voltage to the drain and grounding the source. A cell is typically read by applying a voltage to the word line to which the control gate of the cell is connected, applying a voltage to the bit line to which the drain of the cell is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high, the bit line current will be zero or nearly zero. If the cell is not programmed or erased, the threshold voltage will be relatively low, the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying a voltage to the P-well (substrate) and a negative voltage to the control gate, while allowing the source/drain to float. In another arrangement, a cell may be erased by applying a relatively high voltage to the source, grounding the control gate and allowing the drain to float. In yet another arrangement, the cell is erased by applying a negative voltage to the control gate, applying a voltage to the source and allowing the drain to float. These applied voltages cause the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to either the source or the substrate (P-well) depending on the type of erase being performed.